Cerebras sidesteps AI chip supply bottlenecks with 5nm wafer-scale design

The AI hardware race has mostly been a fight over scarce parts. Cerebras Systems is trying to win it by not needing most of them. The company’s wafer-scale chips avoid high-bandwidth memory (HBM), advanced CoWoS packaging and 3nm manufacturing. Those happen to be three of the tightest chokepoints in the industry right now. A chip built around what it leaves out Cerebras took a different route. Its WSE-3 and the derivative WSE-3T are built on TSMC’s 5nm process node. All of their memory lives on the chip itself as SRAM, rather than on separate HBM stacks. The WSE-3 was announced in March 2024. Its specs read more like a city plan than a chip sheet: 900,000 AI cores, 44 GB of on-chip SRAM and approximately 4 trillion transistors. All of that sits within a 46,225 mm² area. CEO Andrew Feldman has argued the design pays off where it counts most for customers: speed when AI models generate responses. Speaking in June 2026, he described the architecture this way: “the fastest inference in the world by an order of magnitude” The research findings describe Feldman’s claim as boosting token-generation speed while removing the slowdowns typical of GPU-based designs. The backlog behind the bet...