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Meta just solved one of the most expensive headaches in data center computing with a tiny custom chip. The company unveiled Vistara, a purpose-built ASIC that lets old DDR4 memory work inside servers designed exclusively for DDR5, effectively turning yesterday’s hardware into tomorrow’s infrastructure.
How Vistara actually works
Vistara bridges the gap between DDR4 and DDR5 using CXL 2.0, a high-speed interconnect standard that lets additional memory attach through a PCIe 5.0 x16 interface.
Each Vistara chip supports two independent 72-bit DDR4 channels running at up to 3,200 MT/s, with a capacity ceiling of 256 GB per chip. The technical paper, titled “Vistara: Making CXL Real,” was presented at ISCA 2026.
Meta built the chip into a platform called MemServer. Each unit pairs a 158-core AMD EPYC Turin processor with 768 GB of native DDR5-6400 memory and an additional 256 GB of CXL-attached DDR4-2400. That adds up to nearly 1 TB of total available memory per server.
The performance gap between the two memory tiers is substantial. DDR5 delivers 614 GB/s of bandwidth while the DDR4 tier runs at 76 GB/s. Meta’s software handles this by treating the DDR4 pool as a separate NUMA node, letting the operating system place data based on how frequently and how quickly it needs to be accessed.
The economics of memory hoarding
When companies like Meta decommission older servers, they’re left with mountains of perfectly functional DDR4 modules that have no home in modern infrastructure. DDR5-only platforms from AMD and Intel have made those modules orphans overnight.
Buying all-new DDR5 for every server is expensive. Throwing away working DDR4 is wasteful. Vistara addresses both problems with a single piece of silicon.
The strategy is about supplementing primary memory with a cheaper, slower tier for workloads that benefit from large memory pools but don’t need every byte delivered at maximum speed. Database caching, content delivery preprocessing, and certain AI inference tasks fit this profile well.
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